This invention is in the field of solid-state semiconductor memories. Embodiments are more specifically directed to the reliability of such memories.
The ubiquity of solid-state semiconductor memory in electronic systems of many types, from large-scale computing systems and mass data storage (i.e., disk replacement) applications to small-scale controllers and sensors, is well known in the industry. Indeed, the low cost-per-bit now achievable for solid-state memory has enabled modern electronic systems to implement and execute complex computational and control functions in a wide range of applications.
Various types of semiconductor memory are known in the art. Dynamic random access memory (DRAM) and static RAM (SRAM) memories provide high density storage and rapid access, but are volatile in that their contents are lost at power-down; as such, DRAM and SRAM are typically used as data memory. Non-volatile memory technologies include electrically erasable programmable read-only memory (EEPROM) (implemented as either “flash” or non-flash erase memory), mask-programmable read-only memory (ROM), one-time-programmable (OTP) ROM, and ferroelectric memory (FRAM). Non-volatile memory is often used as program memory and mass data storage (e.g., solid-state disk) in modern electronic systems.
The increased memory density for each of these technologies has enabled the implementation of substantial memory capacity within larger scale integrated circuits, such as those including modern complex microprocessors, microcontrollers, digital signal processors, and other large-scale logic circuitry. For example, the so-called “system on a chip” (SoC) typically includes embedded memory of various technologies as program and data memory. Indeed, these memory resources can occupy a relatively large fraction of the chip area of a microcontroller or SoC device. This leverage makes yield loss due to defects in the embedded memories especially costly. Of course, the desire to increase memory density by shrinking the semiconductor device features increases yield pressure, particularly for memory arrays.
Accordingly, many semiconductor memories, whether embedded in a large-scale integrated circuit such as an SoC or in the form of stand-alone memory devices, now include redundant memory cells that can be enabled at manufacturing test to logically replace failed memory cells in the main array. As known in the art, these redundant cells are often arranged as one or more additional columns adjacent to the main memory array, along with the necessary read/write circuitry for those columns. Another approach provides one or more redundant rows of memory cells; in this case, additional sense amplifiers and other read/write circuitry may not be required. In either case, the memory is configured to enable the redundant cells in the event one or more failed cells are identified at manufacturing test. The redundant cells are typically enabled by blowing fuses or programming non-volatile configuration registers in the memory.
As is also well known in the art, semiconductor memories can also be vulnerable to cell failures over the operating life of the integrated circuit. In some cases, for example in DRAM memories, the failures may be “soft” failures in that a cell may sporadically return errored data when read, but then function properly for the remainder of its life. “Hard” failures in which a cell permanently loses the ability to retain data are typically due to physical mechanisms occurring over time, often at the site of a physical defect or contaminant at the particular cell.
As such, some memories include error correction capability to correct such errors that occur over the operating life of the device. Error detection and correction is typically provided by storing each data word as a coded “symbol”, where the number of bits in the symbol is greater than the number of bits in the data word itself, for example with the additional bits stored in additional columns in the array. Depending on the particular error detection and correction technique, decoding of the over-specified symbol can provide the correct data word even if one or more of the data bits of the symbol are erroneous. The level of error detection and correction can range from a simple parity check, to a check sum provided for each data word, up to more complicated non-systematic codes.
For the case of FRAM devices, it has been observed from long-term reliability testing that FRAM cells are somewhat vulnerable to depolarization over time. This depolarization is reflected in data retention failures over the device life. FRAM cells that are constructed as two-transistor two-capacitor (2T-2C) cells are less susceptible to this type of data retention failure than are one-transistor one-capacitor (1T-1C) FRAM cells, because the 2T-2C cell stores data as complementary polarization states on its two capacitors. The complementary polarization states of the 2T-2C cell are reflected as a differential signal when sensed, providing a larger read margin than the 1T-1C cell, which is read by comparing the polarization state of the ferroelectric capacitor against a reference level. While 1T-1C FRAM memory has nearly twice the bit density of 2T-2C FRAM, its reduced read margin is reflected in weaker data retention performance, which limits the use of 1T-1C FRAM in many data-critical applications.